Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution

Author:

Lu Yanan1,Liu Leibo1,Deng Yangdong1,Weng Jian1,Li Zhaoshi1,Deng Chenchen1,Wei Shaojun1

Affiliation:

1. Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, China

Publisher

ACM

Reference15 articles.

1. Reconfigurable Computing Architectures

2. Intel's future with field programmable arrays: We're here to stay. https://newsroom.intel.com/press-kits/2016-idf/#2016-intel-developer-forum. Intel's future with field programmable arrays: We're here to stay. https://newsroom.intel.com/press-kits/2016-idf/#2016-intel-developer-forum.

3. J. Pager R. Jeyapaul and A. Shrivastava. A software scheme for multithreading on CGRAs. ACM Transactions on Embedded Computing Systems (TECS) 14(1):19 2015. 10.1145/2638558 J. Pager R. Jeyapaul and A. Shrivastava. A software scheme for multithreading on CGRAs. ACM Transactions on Embedded Computing Systems (TECS) 14(1):19 2015. 10.1145/2638558

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1. Current Application Fields;Software Defined Chips;2022-11-15

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