Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning-Reference-Cited by-同舟云学术

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
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Author:

Alawieh Mohamad¹,Wang Fa¹,Li Xin¹

Affiliation:

1. Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3062235

Reference26 articles.

1. Semiconductor Industry Associate International Technology Roadmap for Semiconductors 2011. Semiconductor Industry Associate International Technology Roadmap for Semiconductors 2011.

2. Beyond low-order statistical response surfaces

3. Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming

4. Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming

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