Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture-Reference-Cited by-同舟云学术

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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
language:
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Author:

Zhao Qinghang¹,Liu Yongpan¹,Sun Wenyu¹,Zhao Jiaqing²,Yao Hailong¹,Guo Xiaojun²,Yang Huazhong¹

Affiliation:

1. Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China

2. Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China

Funder

National Natural Science Foundation of China

Beijing Innovation Center for Future Chip

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3062227

Reference9 articles.

1. The path to ubiquitous and low-cost organic electronic appliances on plastic

2. Inkjet-configurable gate arrays (IGA);Carrabina Jordi;IEEE Transactions on Emerging Topics in Computing, PP(99):1--1,2016

3. User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects

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1. Design Research on Vibration Tactile Feedback in Vehicle Navigation Information Application;The eighth International Workshop of Chinese CHI;2020-04-26

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