Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation
Author:
Affiliation:
1. Center for Embedded and Cyber-Physical Systems, University of California, Irvine, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3061639.3062243
Reference15 articles.
1. "IEEE Standard SysemC Language Manual IEEE Std 1666--2011 " 2011. "IEEE Standard SysemC Language Manual IEEE Std 1666--2011 " 2011.
2. G. Glaser G. Nitschey and E. Hennig "Temporal Decoupling with Error-Bounded Predictive Quantum Control " in Forum on Specification and Design Languages (FDL) 2015. G. Glaser G. Nitschey and E. Hennig "Temporal Decoupling with Error-Bounded Predictive Quantum Control " in Forum on Specification and Design Languages (FDL) 2015.
3. N. Ventroux and T. Sassolas "A New Parallel SystemC Kernel Leveraging Manycore Architectures " in DATE 2016. N. Ventroux and T. Sassolas "A New Parallel SystemC Kernel Leveraging Manycore Architectures " in DATE 2016.
4. J. H. Weinstock R. Leupers G. Ascheid D. Petras and A. Hoffmann "SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments " in DATE 2016. J. H. Weinstock R. Leupers G. Ascheid D. Petras and A. Hoffmann "SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments " in DATE 2016.
5. W. Chen X. Han and R. Dömer "Out-of-Order Parallel Simulation for ESL Design " in DATE 2012. W. Chen X. Han and R. Dömer "Out-of-Order Parallel Simulation for ESL Design " in DATE 2012.
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