FPD etect

Author:

Das Arnab1ORCID,Krishnamoorthy Sriram2,Briggs Ian1,Gopalakrishnan Ganesh1,Tipireddy Ramakrishna2

Affiliation:

1. University of Utah, Salt Lake City, UT

2. Pacific Northwest National Laboratory, Richland, WA

Abstract

We present FPD etect , a low-overhead approach for detecting logical errors and soft errors affecting stencil computations without generating false positives. We develop an offline analysis that tightly estimates the number of floating-point bits preserved across stencil applications. This estimate rigorously bounds the values expected in the data space of the computation. Violations of this bound can be attributed with certainty to errors. FPD etect helps synthesize error detectors customized for user-specified levels of accuracy and coverage. FPD etect also enables overhead reduction techniques based on deploying these detectors coarsely in space and time. Experimental evaluations demonstrate the practicality of our approach.

Funder

NSF CCF

U.S. Department of Energy, Office of Science, Office of Advanced Scientific Computing Research

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Constrained Precision Tuning;2022 8th International Conference on Control, Decision and Information Technologies (CoDIT);2022-05-17

2. Scalable yet Rigorous Floating-Point Error Analysis;SC20: International Conference for High Performance Computing, Networking, Storage and Analysis;2020-11

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