Author:
Usami Kimiyoshi,Horowitz Mark
Cited by
161 articles.
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1. A New 22 nm ULPLS Architecture to Detect 70 mV Minimum Input, Suitable for IOT Applications;2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech);2023-12-18
2. An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs;2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS);2022-12-01
3. Single Threshold TSO Level Converters for Ultra-Low Power Digital Designs;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24
4. Experimental validation of an analog spiking neural network with STDP learning rule in CMOS technology;2022 IEEE International Conference on Metrology for Extended Reality, Artificial Intelligence and Neural Engineering (MetroXRAINE);2022-10-26
5. A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller;International Journal of Circuit Theory and Applications;2021-11-30