Bayesian Optimization for Efficient Accelerator Synthesis

Author:

Mehrabi Atefeh1,Manocha Aninda2,Lee Benjamin C.3,Sorin Daniel J.1

Affiliation:

1. Duke University, Durham, NC

2. Princeton University

3. University of Pennsylvania

Abstract

Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time that designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches. Prospector permits new studies for heterogeneous accelerators.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Flexi-BOPI: Flexible granularity pipeline inference with Bayesian optimization for deep learning models on HMPSoC;Information Sciences;2024-09

2. Statistical Hardware Design With Multimodel Active Learning;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

3. Sherlock: A Multi-Objective Design Space Exploration Framework;ACM Transactions on Design Automation of Electronic Systems;2022-03-08

4. High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks;IEEE Access;2022

5. Generalizable and interpretable learning for configuration extrapolation;Proceedings of the 29th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of Software Engineering;2021-08-18

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