Energy and Area Efficient Near Field Inductive Coupling
Author:
Affiliation:
1. School of EECS, Washington State University, Pullman, WA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3130218.3130224
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2. W. R. Davis etal "Demystifying 3D ICs: the pros and cons of going vertical " in IEEE Design and Test of Computers vol. 22 6 pp. 498--510 Nov.-Dec. 2005. 10.1109/MDT.2005.136 W. R. Davis et al. "Demystifying 3D ICs: the pros and cons of going vertical " in IEEE Design and Test of Computers vol. 22 6 pp. 498--510 Nov.-Dec. 2005. 10.1109/MDT.2005.136
3. 3D-Stacked Memory Architectures for Multi-core Processors
4. TSV Redundancy: Architecture and Design Issues in 3-D IC
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1. Sparse 3-D NoCs with Inductive Coupling;Proceedings of the 56th Annual Design Automation Conference 2019;2019-06-02
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