System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip-Reference-Cited by-同舟云学术

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

Published:2017-10-19 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip
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Author:

Yoon Young Jin¹,Mantovani Paolo²,Carloni Luca P.²

Affiliation:

1. Department of Computer Science, Columbia University, New York, New York and Intel Corporation, Hillsboro, OR

2. Department of Computer Science, Columbia University, New York, New York

Funder

National Science Foundation

Defense Advanced Research Projects Agency

Semiconductor Research Corporation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3130218.3130238

Reference23 articles.

1. J Bachrach etal 2012 Chisel Constructing hardware in a Scala Embedded Language In Design Automation Conference (DAC) 1212--1221 10.1145/2228360.2228584 J Bachrach et al 2012 Chisel Constructing hardware in a Scala Embedded Language In Design Automation Conference (DAC) 1212--1221 10.1145/2228360.2228584

2. K Barker etal 2013 PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute http//hpcpnnl.gov/projects/PERFECT/ K Barker et al 2013 PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute http//hpcpnnl.gov/projects/PERFECT/

3. D Becker 2012 Efficient Microarchitecture for Network-on-Chip Routers PhD Dissertation Stanford University D Becker 2012 Efficient Microarchitecture for Network-on-Chip Routers PhD Dissertation Stanford University

4. Invited - The case for embedded scalable platforms

5. M. Dall'Osso et al. 2003. xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs. 45--48. M. Dall'Osso et al. 2003. xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs. 45--48.

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