SuperNet
Author:
Affiliation:
1. University of New South Wales, Sydney, Australia
2. Google Inc.
3. Karlsruhe Institute of Technology, Karlsruhe, Germany
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2744769.2744912
Reference27 articles.
1. Synopsys "Design Solutions for 20nm and Beyond White Paper." http://www.synopsys.com/. Synopsys "Design Solutions for 20nm and Beyond White Paper." http://www.synopsys.com/.
2. Circuit design challenges at the 14nm technology node
3. "Semico Research - How Reducing Verification and Validation Time Can Improve Profitability." http://www.semico.com/. "Semico Research - How Reducing Verification and Validation Time Can Improve Profitability." http://www.semico.com/.
4. A 2 Tb/s 6$\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS
5. Energy characterization of a tiled architecture processor with on-chip networks
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1. SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
2. Power efficient network selector placement in control plane of multiple networks-on-chip;The Journal of Supercomputing;2021-10-25
3. Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router;2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS);2021-06-28
4. Resilient System-on-Chip Designs With NoC Fabrics;IEEE Transactions on Information Forensics and Security;2020
5. Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
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