Boolean logic optimization in majority-inverter graphs-Reference-Cited by-同舟云学术

Boolean logic optimization in majority-inverter graphs

Published:2015-06-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 52nd Annual Design Automation Conference
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Author:

Amarù Luca¹,Gaillardon Pierre-Emmanuel¹,De Micheli Giovanni¹

Affiliation:

1. Integrated Systems Laboratory (LSI), EPFL, Switzerland

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2744769.2744806

Reference19 articles.

1. A. Mishchenko etal Using simulation and satisfiability to compute flexibilities in Boolean networks IEEE TCAD 25.5 (2006): 743-755. 10.1109/TCAD.2005.860955 A. Mishchenko et al. Using simulation and satisfiability to compute flexibilities in Boolean networks IEEE TCAD 25.5 (2006): 743-755. 10.1109/TCAD.2005.860955

2. A. Mishchenko etal Scalable don't-care-based logic optimization and resynthesis ACM TRETS 4.4 (2011): 34. 10.1145/2068716.2068720 A. Mishchenko et al. Scalable don't-care-based logic optimization and resynthesis ACM TRETS 4.4 (2011): 34. 10.1145/2068716.2068720

3. BDS: a BDD-based logic optimization system

4. BDD-based logic synthesis for LUT-based FPGAs

5. BDS-MAJ

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