The load slice core microarchitecture-Reference-Cited by-同舟云学术

The load slice core microarchitecture

Published:2015-06-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 42nd Annual International Symposium on Computer Architecture
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Author:

Carlson Trevor E.¹,Heirman Wim²,Allam Osman³,Kaxiras Stefanos¹,Eeckhout Lieven³

Affiliation:

1. Uppsala University, Sweden

2. Intel, ExaScience Lab

3. Ghent University, Belgium

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2749469.2750407

Reference42 articles.

1. ARM "2GHz capable Cortex-A9 dual core processor implementation " http://www.arm.com/files/downloads/Osprey_Analyst_Presentation_v2a.pdf archived at the Internet Archive (http://archive.org). ARM "2GHz capable Cortex-A9 dual core processor implementation " http://www.arm.com/files/downloads/Osprey_Analyst_Presentation_v2a.pdf archived at the Internet Archive (http://archive.org).

2. ARM "ARM Cortex-A7 processor " http://www.arm.com/products/processors/cortex-a/cortex-a7.php. ARM "ARM Cortex-A7 processor " http://www.arm.com/products/processors/cortex-a/cortex-a7.php.

3. "Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense

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