Parallel gate-level circuit simulation on shared memory architectures

Author:

Bagrodia Rajive1,Chen Yu-an1,Jha Vikas1,Sonpar Nicki1

Affiliation:

1. Computer Science Department, University of California at Los Angeles, Los Angeles, CA

Abstract

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

Publisher

Association for Computing Machinery (ACM)

Reference14 articles.

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2. Breaking the barrier of parallel simulation of digital systems

3. Acyclic multi-way partitioning of Boolean networks

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