I RON M AN-Reference-Cited by-同舟云学术

I RON M AN

Published:2021-06-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2021 on Great Lakes Symposium on VLSI
language:
Short-container-title:

Author:

Wu Nan¹,Xie Yuan¹,Hao Cong²

Affiliation:

1. University of California, Santa Barbara, Santa Barbara, CA, USA

2. Georgia Institute of Technology, Atlanda, GA, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3453688.3461495

Reference22 articles.

1. Cadance. Accessed: 2021. Cadance Stratus High-Level Synthesis. https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html. Cadance. Accessed: 2021. Cadance Stratus High-Level Synthesis. https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html.

2. Jason Cong et al. 2012. Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. In 49th DAC. Jason Cong et al. 2012. Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. In 49th DAC.

3. Steve Dai et al. 2018. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In FCCM. Steve Dai et al. 2018. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In FCCM.

4. Will Hamilton et al. 2017. Inductive representation learning on large graphs. In NeurIPS. Will Hamilton et al. 2017. Inductive representation learning on large graphs. In NeurIPS.

5. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis;Yuko Hara;JIP,2009

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