EPEX-Reference-Cited by-同舟云学术

EPEX

Published:2021-06-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2021 on Great Lakes Symposium on VLSI
language:
Short-container-title:

Author:

Klemmer Lucas¹,Große Daniel¹

Affiliation:

1. Johannes Kepler University, Linz, Austria

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3453688.3461497

Reference30 articles.

1. 2021. GitHub - VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation. https://github.com/SpinalHDL/VexRiscv. 2021. GitHub - VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation. https://github.com/SpinalHDL/VexRiscv.

2. 2021. OneSpin 360 DV RISC-V Verification App. https://www.onespin.com/ solutions/risc-v. 2021. OneSpin 360 DV RISC-V Verification App. https://www.onespin.com/ solutions/risc-v.

3. 2021. RISC-V Compliance Task Group. https://github.com/riscv/riscv-compliance. 2021. RISC-V Compliance Task Group. https://github.com/riscv/riscv-compliance.

4. 2021. RISC-V Formal Verification Framework. https://github.com/YosysHQ/riscv-formal. 2021. RISC-V Formal Verification Framework. https://github.com/YosysHQ/riscv-formal.

5. 2021. RISC-V ISA Tests. https://github.com/riscv/riscv-tests. 2021. RISC-V ISA Tests. https://github.com/riscv/riscv-tests.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V;Proceedings of the Great Lakes Symposium on VLSI 2022;2022-06-06

2. Model Checking for AlphaCode-Generated Programs;2022 7th International Conference on Intelligent Computing and Signal Processing (ICSP);2022-04-15