Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations
Author:
Affiliation:
1. RWTH Aachen University, Aachen, Germany
2. Intrinsic-ID, Eindhoven, Netherlands
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3240765.3240836
Reference34 articles.
1. V. Sharma etal "Ultra low-energy SRAM design for smart ubiquitous sensors " IEEE Micro pp. 10--24 Sept.-Oct. 2012. 10.1109/MM.2012.58 V. Sharma et al. "Ultra low-energy SRAM design for smart ubiquitous sensors " IEEE Micro pp. 10--24 Sept.-Oct. 2012. 10.1109/MM.2012.58
2. M. Qazi M. E. Sinangil and A. P. Chandrakasan "Challenges and directions for low-voltage SRAM " IEEE Design & Test Comput. pp. 32--43 Jan--Feb. 2011. 10.1109/MDT.2010.115 M. Qazi M. E. Sinangil and A. P. Chandrakasan "Challenges and directions for low-voltage SRAM " IEEE Design & Test Comput. pp. 32--43 Jan--Feb. 2011. 10.1109/MDT.2010.115
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1. A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04
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