PolySA

Author:

Cong Jason1,Wang Jie1

Affiliation:

1. University of California

Funder

NSF ICN-WEN

NSF InTrans Award

Publisher

ACM

Reference25 articles.

1. Alfred V. Aho Monica S. Lam Ravi Sethi and Jeffrey D. Ullman. 2006. Compilers: Principles Techniques and Tools (2nd Edition). Addison-Wesley Longman Publishing Co. Inc. Boston MA USA. Alfred V. Aho Monica S. Lam Ravi Sethi and Jeffrey D. Ullman. 2006. Compilers: Principles Techniques and Tools (2nd Edition). Addison-Wesley Longman Publishing Co. Inc. Boston MA USA.

2. Amazon. 2018. Amazon EC2 F1 Instances. (2018). https://aws.amazon.com/ec2/instance-types/f1 Amazon. 2018. Amazon EC2 F1 Instances. (2018). https://aws.amazon.com/ec2/instance-types/f1

3. Cédric Bastoul Albert Cohen Sylvain Girbal and et al. 2003. Putting Polyhedral Loop Transformations to Work. In LCPC. College Station Texas 209--225. Cédric Bastoul Albert Cohen Sylvain Girbal and et al. 2003. Putting Polyhedral Loop Transformations to Work. In LCPC. College Station Texas 209--225.

4. Mohamed-Walid Benabderrahmane Louis-Noël Pouchet and etal 2010. The Polyhedral Model is More Widely Applicable Than You Think. In ETAPS (CC'10/ETAPS'10). Springer-Verlag Berlin Heidelberg 283--303. 10.1007/978-3-642-11970-5_16 Mohamed-Walid Benabderrahmane Louis-Noël Pouchet and et al. 2010. The Polyhedral Model is More Widely Applicable Than You Think. In ETAPS (CC'10/ETAPS'10). Springer-Verlag Berlin Heidelberg 283--303. 10.1007/978-3-642-11970-5_16

5. Uday Bondhugula J. Ramanujam and P. Sadayappan. 2007. Automatic Mapping of Nested Loops to FPGAS. In PPoPP. ACM New York NY USA 101--111. 10.1145/1229428.1229446 Uday Bondhugula J. Ramanujam and P. Sadayappan. 2007. Automatic Mapping of Nested Loops to FPGAS. In PPoPP . ACM New York NY USA 101--111. 10.1145/1229428.1229446

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1. HiEval: A scheduling performance estimation approach for spatial accelerators via hierarchical abstraction;Journal of Systems Architecture;2024-02

2. MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

3. TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design;ACM Transactions on Reconfigurable Technology and Systems;2023-12-05

4. Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04

5. A Survey of Design and Optimization for Systolic Array-based DNN Accelerators;ACM Computing Surveys;2023-08-25

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