RAIL: Predictable, Low Tail Latency for NVMe Flash

Author:

Litz Heiner1,Gonzalez Javier2,Klimovic Ana3,Kozyrakis Christos4

Affiliation:

1. University of California, Santa Cruz, CA

2. Samsung

3. ETH Zürich, Switzerland

4. Stanford University, CA

Abstract

Flash-based storage is replacing disk for an increasing number of data center applications, providing orders of magnitude higher throughput and lower average latency. However, applications also require predictable storage latency. Existing Flash devices fail to provide low tail read latency in the presence of write operations. We propose two novel techniques to address SSD read tail latency, including Redundant Array of Independent LUNs (RAIL) which avoids serialization of reads behind user writes as well as latency-aware hot-cold separation (HC) which improves write throughput while maintaining low tail latency. RAIL leverages the internal parallelism of modern Flash devices and allocates data and parity pages to avoid reads getting stuck behind writes. We implement RAIL in the Linux Kernel as part of the LightNVM Flash translation layer and show that it can reduce read tail latency by 7× at the 99.99th percentile, while reducing relative bandwidth by only 33%.

Funder

Samsung

NSF

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture

Reference82 articles.

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