Fast Instruction Cache Simulation is Trickier than You Think-Reference-Cited by-同舟云学术

Fast Instruction Cache Simulation is Trickier than You Think

Published:2023-01-17 Issue: Volume: Page:
ISSN:
Container-title:DroneSE and RAPIDO: System Engineering for constrained embedded systems
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Author:

Badaroux Marie¹^ORCID,Dumas Julie¹^ORCID,Petrot Frederic¹^ORCID

Affiliation:

1. Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France

Funder

Agence Nationale de la Recherche

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3579170.3579261

Reference25 articles.

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4. Christian Bienia , Sanjeev Kumar , Jaswinder Pal Singh , and Kai Li . 2008 . The PARSEC benchmark suite: Characterization and architectural implications . In Proceedings of the 17th international conference on Parallel architectures and compilation techniques. IEEE, 72–81 . Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques. IEEE, 72–81.

5. Hadi Brais , Rajshekar Kalayappan , and Preeti Panda . 2020. A Survey of Cache Simulators. ACM Computing Surveys (CSUR) 53 (02 2020 ), 1–32. Hadi Brais, Rajshekar Kalayappan, and Preeti Panda. 2020. A Survey of Cache Simulators. ACM Computing Surveys (CSUR) 53 (02 2020), 1–32.