Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs

Abstract

At the 3nm node, a hybrid-row-height design paradigm has emerged for better power efficiency and performance optimization. A diverse cell library that includes multiple variants of a cell with different fin counts is available. Instead of using cells with the same fin count for the entire chip, a design may combine cells with two different fin counts. Cells with the same fin count can be laid down in the same row resulting in a chip with hybrid row heights. With this brand-new design paradigm, revisiting and revamping the conventional VLSI placement flow becomes necessary. There were attempts that addressed the placement problem associated with hybrid-row-height design at the global placement stage or the placement legalization stage. In this work, we first propose an effective detailed placement approach suitable for hybrid-row-height designs and then conduct a comprehensive study to evaluate the different options of forming a complete hybrid-row-height design placement flow. For the first time, the advantage of considering the row configuration early on in the global placement stage is confirmed. Besides, our proposed detailed placement approach can improve the final half-perimeter wirelength by over 7% on average which more than double the improvement obtainable by a basic detailed placement algorithm similar to the well-known FastDP.