Affiliation:
1. Carleton Univ.
2. Universidad de Buenos Aires
Abstract
Alfa-1 is a simulated computer designed for computer organization
courses. Alfa-1 and its accompanying toolkit allow students to
acquire practical insights into developing hardware by extending
existing components. The DEVS formalism is used to model individual
components and to integrate them into a hierarchy that describes
the detailed behavior of different levels of a computer's
architecture. We introduce Alfa-1 and the toolkit, show how to
extend existing components, and describe how to use Alfa-1 for
educational purposes. We also explain how to assemble, link, and
execute applications and how to test new extensions usingthe
testing tools.
Publisher
Association for Computing Machinery (ACM)
Reference36 articles.
1. BEIZER B. 1990. Software Testing Techniques 2nd ed. Van Nostrand Reinhold New York NY. BEIZER B. 1990. Software Testing Techniques 2nd ed. Van Nostrand Reinhold New York NY.
2. BEVILACQUA R. GOMEZ L. AND GOMEZ S. 2000. The PROVIR virtual processor. M. Sc. Thesis Dep. deComputacion Facultad de Ciencias Exactas y Naturales Univ. de Buenos Aires (in Spanish). BEVILACQUA R. GOMEZ L. AND GOMEZ S. 2000. The PROVIR virtual processor. M. Sc. Thesis Dep. deComputacion Facultad de Ciencias Exactas y Naturales Univ. de Buenos Aires (in Spanish).
3. PROTEUS: A High-Performance Parallel-Architecture Simulator
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