High-Level Approaches to Hardware Security: A Tutorial

Author:

Pearce Hammond1ORCID,Karri Ramesh1ORCID,Tan Benjamin2ORCID

Affiliation:

1. New York University, Brooklyn, New York, USA

2. University of Calgary, Calgary, Alberta, Canada

Abstract

Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits or take advantage of “backdoors” in a design. Unintended design bugs can also result in security weaknesses. This tutorial paper provides an introduction to the domain of hardware security through two pedagogical examples of hardware security problems. The first is a walk-through of the scan chain-based side channel attack. The second is a walk-through of logic locking of digital designs. The tutorial material is accompanied by open access digital resources that are linked in this article.

Funder

NSF

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02

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