Author:
Cong Jason,Li Peng,Xiao Bingjun,Zhang Peng
Cited by
14 articles.
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1. Optimizing Stencil Computation on Multi-core DSPs;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12
2. Across Time and Space:
Senju
’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2023-11-29
3. Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
4. Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks;Proceedings of the International Conference on Parallel Architectures and Compilation Techniques;2022-10-08
5. Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components;ACM Transactions on Reconfigurable Technology and Systems;2021-09-30