Toward a Human-Readable State Machine Extraction

Author:

Brunner Michaela1ORCID,Hepp Alexander1,Baehr Johanna1,Sigl Georg2

Affiliation:

1. Technical University of Munich, Munich, Germany

2. Technical University of Munich and Fraunhofer Institute for Applied and Integrated Security, Munich, Germany

Abstract

The target of sequential reverse engineering is to extract the state machine of a design. Sequential reverse engineering of a gate-level netlist consists of the identification of so-called state flip-flops (sFFs), as well as the extraction of the state machine. The second step can be solved with an exact approach if the correct sFFs and the correct reset state are provided. For the first step, several more or less heuristic approaches exist. This work investigates sequential reverse engineering with the objective of a human-readable state machine extraction. A human-readable state machine reflects the original state machine and is not overloaded by additional design information. For this purpose, the work derives a systematic categorization of sFF sets, based on properties of single sFFs and their sets. These properties are determined by analyzing the degrees of freedom in describing state machines as the well-known Moore and Mealy machines. Based on the systematic categorization, this work presents an sFF set definition for a human-readable state machine, categorizes existing sFF identification strategies, and develops four post-processing methods. The results show that post-processing predominantly improves the outcome of several existing sFF identification algorithms.

Funder

Fraunhofer High Performance Center Secure Intelligent Systems

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03

2. On the Malicious Potential of Xilinx’ Internal Configuration Access Port (ICAP);ACM Transactions on Reconfigurable Technology and Systems;2023-11-17

3. Timing Camouflage Enabled State Machine Obfuscation;2022 IEEE Physical Assurance and Inspection of Electronics (PAINE);2022-10-25

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