1. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
2. Clock Optimization Techniques;2022 IEEE 5th International Conference on Electronics Technology (ICET);2022-05-13
3. Hybrid Multisource Clock Tree Synthesis;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28
4. Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV;Proceedings of the 2020 International Symposium on Physical Design;2020-03-20
5. Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew;Proceedings of the 24th Asia and South Pacific Design Automation Conference;2019-01-21