1. A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. Detailed Placement for Dedicated LUT-Level FPGA Interconnect;ACM Transactions on Reconfigurable Technology and Systems;2022-12-09
3. Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
4. Mixed-Cell-Height Standard Cell Placement Legalization;Proceedings of the on Great Lakes Symposium on VLSI 2017;2017-05-10
5. Detailed placement for modern FPGAs using 2D dynamic programming;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07