Fixed-Point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis

Author:

Li Carol Jingyi1,Li Xiangwei2,Lou Binglei1,Jin Craig T.1,Boland David1,Leong Philip H.W.3

Affiliation:

1. The University of Sydney, Faculty of Engineering, School of Electrical and Information Engineering, Australia

2. Nanyang Technological University, School of Computer Science and Engineering, Singapore

3. The University of Sydney, The University of Sydney Nano Institute, Faculty of Engineering, School of Electrical and Information Engineering, Australia

Abstract

The spectral correlation density (SCD) is an important tool in cyclostationary signal detection and classification. Even using efficient techniques based on the fast Fourier transform (FFT), real-time implementations are challenging because of the high computational complexity. A key dimension for computational optimization lies in minimizing the wordlength employed. In this paper, we analyze the relationship between wordlength and signal-to-quantization noise in fixed-point implementations of the SCD function. A canonical SCD estimation algorithm, the FFT accumulation method (FAM) using fixed-point arithmetic is studied. We derive closed-form expressions for SQNR and compare them at wordlengths ranging from 14 to 26 bits. The differences between the calculated SQNR and bit-exact simulations are less than 1 dB. Furthermore, an HLS-based FPGA design is implemented on a Xilinx Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. Using less than 25% of the logic fabric on the device, it consumes 7.7 W total on-chip power and has a power efficiency of 12.4 GOPS/W, which is an order of magnitude improvement over an Nvidia Tesla K40 graphics processing unit (GPU) implementation. In terms of throughput, it achieves 50 MS/sec, which is a speedup of 1.6 over a recent optimized FPGA implementation.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

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5. Digital implementations of spectral correlation analyzers

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