hXDP

Author:

Brunella Marco Spaziani1,Belocchi Giacomo1,Bonola Marco2,Pontarelli Salvatore3,Siracusano Giuseppe4,Bianchi Giuseppe5,Cammarano Aniello6,Palumbo Alessandro5,Petrucci Luca5,Bifulco Roberto4

Affiliation:

1. Axbryd/University of Rome Tor Vergata, Rome, Italy

2. Axbryd/CNIT, Rome, Italy

3. Axbryd/University of Rome La Sapienza, Rome, Italy

4. NEC Laboratories Europe, Heidelberg, Germany

5. University of Rome Tor Vergata, Rome, Italy

6. Axbryd, Rome, Italy

Abstract

The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-programmed after deployment, to adapt to changing application requirements, and can achieve both high throughput and low latency when implementing packet processing tasks. However, they have limited resources that may need to be shared among diverse applications, and programming them is difficult and requires hardware design expertise. We present hXDP, a solution to run on FPGAs software packet processing tasks described with the eBPF technology and targeting the Linux's eXpress Data Path. hXDP uses only a fraction of the available FPGA resources, while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized, or completely removed, when targeting a purpose-built FPGA design, thereby significantly improving performance. We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation runs at 156.25MHz and uses about 15% of the FPGA resources. Despite these modest requirements, it can run dynamically loaded programs, achieves the packet processing throughput of a high-end CPU core, and provides a 10X lower packet forwarding latency.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

Reference32 articles.

1. P4-NetFPGA. https://github.com/NetFPGA/P4-NetFPGA-public/wiki. P4-NetFPGA. https://github.com/NetFPGA/P4-NetFPGA-public/wiki.

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3. P4

4. Forwarding metamorphosis

5. A VLIW packet manipulator processor. In 2018 European Conference on Networks and Communications (EuCNC);Brunella M.S.;IEEE,2018

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