A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies
Author:
Affiliation:
1. Research Scholar, E&CE Dept., MNNIT, Allahabad, India
2. Professor, E&CE Dept., MNNIT, Allahabad, India
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2818567.2818676
Reference13 articles.
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3. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
4. Paulo Butzen , "Leakage current modeling in Sub-micrometer CMOS complex gates" , Research Thesis , German university for higher Studies , Sep. 2006 Paulo Butzen, "Leakage current modeling in Sub-micrometer CMOS complex gates", Research Thesis, German university for higher Studies, Sep. 2006
5. Scaling of stack effect and its application for leakage reduction
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