Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures
Author:
Affiliation:
1. IETR, INSA, UBL Rennes, France
2. Kalray & IETR, Montbonnot-Saint-Martin, France
3. Lab-STICC, UBS, Lorient, France
4. Montbonnot-Saint-Martin, France
Funder
CNRS, GdR ISIS
Publisher
ACM Press
Reference18 articles.
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3. F. Conti, D. Palossi, A. Marongiu, D. Rossi, and L. Benini. 2016. Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. In Design, Automation & Test in Europe Conference & Exhibition. IEEE, 1201--1206.
4. B. D. de Dinechin, R. Ayrignac, P.-E. Beaucamps, P. Couvert, B. Ganne, P. G. de Massas, F. Jacquet, S. Jones, N. M. Chaisemartin, F. Riss, et al. 2013. A clustered manycore processor architecture for embedded and accelerated applications. In High Performance Extreme Computing Conference (HPEC). IEEE, 1--6.
5. K. Desnos, M. Pelcat, J.-F. Nezan, S.S. Bhattacharyya, and S. Aridhi. 2013. PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Re-configuration. In Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). IEEE, 41--48.
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