A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems-Reference-Cited by-同舟云学术

A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems

Published:2023-08 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2023 International Conference on Neuromorphic Systems
language:
Short-container-title:

Author:

Romero Bermudez Juan Pablo¹^ORCID,Plana Luis A.²^ORCID,Rowley Andrew²^ORCID,Hessel Mikael¹^ORCID,Pedersen Jens E.¹^ORCID,Furber Steve²^ORCID,Conradt Jorg¹^ORCID

Affiliation:

1. Royal Institute of Technology, Stockholm, Sweden

2. The University of Manchester, Manchester, United Kingdom

Funder

EC Horizon 2020 Framework Programme

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3589737.3605969

Reference9 articles.

1. Andrew P. Davison , Daniel Brüderle , Jochen M. Eppler , Jens Kremkow , Eilif B. Müller , Dejan Pecevski , Laurent Udo Perrinet, and Pierre Yger . 2008 . PyNN: A Common Interface for Neuronal Network Simulators. Frontiers in Neuroinformatics 2 (2008). Andrew P. Davison, Daniel Brüderle, Jochen M. Eppler, Jens Kremkow, Eilif B. Müller, Dejan Pecevski, Laurent Udo Perrinet, and Pierre Yger. 2008. PyNN: A Common Interface for Neuronal Network Simulators. Frontiers in Neuroinformatics 2 (2008).

2. Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System

3. SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor

4. AEStream: Accelerated event-based processing with coroutines

5. Luis A. Plana and Steve Furber . 2017 . Interfacing AER devices to SpiNNaker using an FPGA. https://spinnakermanchester.github.io/docs/fpga_aer/ Luis A. Plana and Steve Furber. 2017. Interfacing AER devices to SpiNNaker using an FPGA. https://spinnakermanchester.github.io/docs/fpga_aer/