Affiliation:
1. The Catholic University of Korea
2. Processor Architecture Lab., Samsung Electronics
Abstract
The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42~101 % and excels the toroidal mesh-based system by 4~14%.
Publisher
Association for Computing Machinery (ACM)
Reference11 articles.
1. IEEE Computer Society IEEE Standard for Scalable Coherent Interface(SCI) Inst. of Electrical and Electronics Engineers Aug. 1993. IEEE Computer Society IEEE Standard for Scalable Coherent Interface(SCI) Inst. of Electrical and Electronics Engineers Aug. 1993.