Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in Intermittently-Powered IoT Devices

Author:

Jayakumar Hrishikesh1ORCID,Raha Arnab1,Stevens Jacob R.1,Raghunathan Vijay1

Affiliation:

1. Purdue University, West Lafayette, IN

Abstract

Forecasts project that by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), most of which will operate untethered and unplugged. While environmental energy harvesting is a promising solution to power these IoT edge devices, it introduces new complexities due to the unreliable nature of ambient energy sources. In the presence of an unreliable power supply, frequent checkpointing of the system state becomes imperative, and recent research has proposed the concept of in-situ checkpointing by using ferroelectric RAM (FRAM), an emerging non-volatile memory technology, as unified memory in these systems. Even though an entirely FRAM-based solution provides reliability, it is energy inefficient compared to SRAM due to the higher access latency of FRAM. On the other hand, an entirely SRAM-based solution is highly energy efficient but is unreliable in the face of power loss. This paper advocates an intermediate approach in hybrid FRAM-SRAM microcontrollers that involves judicious memory mapping of program sections to retain the reliability benefits provided by FRAM while performing almost as efficiently as an SRAM-based system. We propose an energy-aware memory mapping technique that maps different program sections to the hybrid FRAM-SRAM microcontroller such that energy consumption is minimized without sacrificing reliability. Our technique consists of eM-map , which performs a one-time characterization to find the optimal memory map for the functions that constitute a program and energy-align , a novel hardware-software technique that aligns the system’s powered-on time intervals to function execution boundaries, which results in further improvements in energy efficiency and performance. Experimental results obtained using the MSP430FR5739 microcontroller demonstrate a significant performance improvement of up to 2x and energy reduction of up to 20% over a state-of-the-art FRAM-based solution. Finally, we present a case study that shows the implementation of our techniques in the context of a real IoT application.

Funder

National Science Foundation

Semiconductor Research Corporation

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Cited by 38 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Energy Harvesting-Supported Efficient Low-Power ML Processing with Adaptive Checkpointing and Intermittent Computing;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05

2. LACT: Liveness-Aware Checkpointing to reduce checkpoint overheads in intermittent systems;Journal of Systems Architecture;2024-08

3. TinyBFT: Byzantine Fault-Tolerant Replication for Highly Resource-Constrained Embedded Systems;2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS);2024-05-13

4. SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems;2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO);2024-03-02

5. Ensuring consistent recovery under power failure with minimal NVM write overhead;Journal of Systems Architecture;2024-03

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