1. Chip Planning;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022
2. Floorplanning;Layoutsynthese elektronischer Schaltungen;2016
3. Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs;Integration;2013-06
4. Chip Planning;VLSI Physical Design: From Graph Partitioning to Timing Closure;2011
5. Pin Assignment Using Stochastic Local Search Constraint Programming;Principles and Practice of Constraint Programming - CP 2009;2009