Chip placement in a reticle for multiple-project wafer fabrication

Abstract

Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼ 29% fewer wafers and 8%∼ 19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]