Formal Verification of Optimizing Transformations during High-level Synthesis-Reference-Cited by-同舟云学术

Formal Verification of Optimizing Transformations during High-level Synthesis

Published:2019-02-14 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference)
language:
Short-container-title:

Author:

Chouksey Ramanuj¹,Karfa Chandan¹,Bhaduri Purandar¹

Affiliation:

1. Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, Guwahati, Assam, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3299771.3299797

Reference14 articles.

1. Verification of Code Motion Techniques Using Value Propagation;Banerjee Kunal;IEEE TCAD,2014

2. Ramanuj Chouksey Chandan Karfa Kunal Banerjee Pankj Kalita and Purandar Bhaduri. forthcoming. A Counter-Example Generation Procedure for Path based Equivalence Checkers. IET Softeware (forthcoming). Ramanuj Chouksey Chandan Karfa Kunal Banerjee Pankj Kalita and Purandar Bhaduri. forthcoming. A Counter-Example Generation Procedure for Path based Equivalence Checkers. IET Softeware (forthcoming).

3. Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. 2017. Translation Validation of Loop Invariant Code Optimizations Involving False Computations. In VDAT. 767--778. Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. 2017. Translation Validation of Loop Invariant Code Optimizations Involving False Computations. In VDAT. 767--778.

4. Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. 2018. Translation Validation of Code Motion Transformations Involving Loops. IEEE TCAD (2018). Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. 2018. Translation Validation of Code Motion Transformations Involving Loops. IEEE TCAD (2018).

5. Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. forthcoming. Improving Performance of a Path-Based Equivalence Checker using Counter-Examples. In VLSID. Ramanuj Chouksey Chandan Karfa and Purandar Bhaduri. forthcoming. Improving Performance of a Path-Based Equivalence Checker using Counter-Examples. In VLSID.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-thread Simulation-based Equivalence Checking between SIM and RTI;Proceedings of the 4th International Conference on Computer Science and Application Engineering;2020-10-15