DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design

Author:

Gao Yizhao1,Zhang Baoheng1,Qi Xiaojuan1,So Hayden Kwok-Hay1

Affiliation:

1. University of Hong Kong, Hong Kong

Funder

Research Grants Council, University Grants Committee

Environment and Conservation Fund

Publisher

ACM

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2. DyPIM: Dynamic-Inference-Enabled Processing - In-Memory Accelerator;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

4. MiniMalloc: A Lightweight Memory Allocator for Hardware-Accelerated Machine Learning;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4;2023-03-25

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