An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)-Reference-Cited by-同舟云学术

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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

Published:2004 Issue: Volume: Page:
ISSN:
Container-title:Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
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Author:

Dadda Luigi,Macchetti Marco,Owen Jeff

Publisher

ACM Press

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Custom ASIC Design for SHA-256 Using Open-Source Tools;Computers;2023-12-25

2. An Unrolled and Pipelined Architecture for SHA2 Family of Hash Functions on FPGA;2023 16th International Conference on Information Security and Cryptology (ISCTürkiye);2023-10-18

3. High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications;2023 IEEE European Test Symposium (ETS);2023-05-22

4. BitCracker: BitLocker meets GPUs;International Journal of Information Security;2022-05-03

5. A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications;2021 International Conference on Advanced Technologies for Communications (ATC);2021-10-14

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