Does SoC Hardware Development Become Agile by Saying So: A Literature Review and Mapping Study

Author:

Rautakoura Antti1ORCID,Hämäläinen Timo1ORCID

Affiliation:

1. Tampere University, Tampere, Pirkanmaa, Finland

Abstract

The success of agile development methods in software development has raised interest in System-on-Chip (SoC) design, which involves high architectural and development process complexity under time and project management pressure. This article discovers the current state of agile hardware development with the questions (1) how well literature covers the SoC development process, (2) what agile methods and practices are applied or (3) what proposals are made to increase the agility, and (4) what is the impact for the SoC community. To answer the questions, a mapping study and literature review were performed. Seven hundred thirty papers were first studied, and eventually, after a rigorous filtering process, 25 papers were thoroughly analyzed. The results show that the popular agile SW development methods are applied in 5 cases, ideas adapted from the agile Hardware manifesto in 9 cases, and 11 cases do not define the Agile HW development method. Most of the papers address shorter development time by better methodologies and tools that indirectly shape the SoC development toward agility. The focus of agile hardware development is mostly on the SoC artifacts and methodological improvements have not been quantified. However, the literature indicates a significant impact on many academic chip prototypes. The challenges are better understood and the interest in agile methods is clearly increasing. The methodological gaps in the prevalent situation encourage further research and more accurate reporting of the development in addition to the SoC artifacts.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Measuring the SoC development process quality with Fault-slip-Through methodology;2024 13th Mediterranean Conference on Embedded Computing (MECO);2024-06-11

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3. A Pipelined AES and SM4 Hardware Implementation for Multi-tasking Virtualized Environments;Lecture Notes in Computer Science;2024

4. Memory Mapped I/O Register Test Case Generator for Large Systems-on-Chip;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

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