Affiliation:
1. State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), CAS, China
2. Carnegie Mellon University, United States
3. University of Science and Technology of China, China
4. Inria, France
5. National Key Laboratory for Novel Software Technology, Nanjing University, China
Abstract
Architectural Design Space Exploration (DSE) is a notoriously difficult problem due to the exponentially large size of the design space and long simulation times. Previously, many studies proposed to formulate DSE as a regression problem which predicts architecture responses (e.g., time, power) of a given architectural configuration. Several of these techniques achieve high accuracy, though often at the cost of significant simulation time for training the regression models.
We argue that the information the architect mostly needs during the DSE process is whether a given configuration will perform better than another one in the presences of design constraints, or better than any other one seen so far, rather than precisely estimating the performance of that configuration.
Based on this observation, we propose a novel rankingbased approach to DSE where we train a model to predict which of two architecture configurations will perform best. We show that, not only this ranking model more accurately predicts the relative merit of two architecture configurations than an ANN-based state-of-the-art regression model, but also that it requires much fewer training simulations to achieve the same accuracy, or that it can be used for and is even better at quantifying the performance gap between two configurations
We implement the framework for training and using this model, called ArchRanker, and we evaluate it on several DSE scenarios (unicore/multicore design spaces, and both time and power performance metrics). We try to emulate as closely as possible the DSE process by creating constraint-based scenarios, or an iterative DSE process. We find that ArchRanker makes 29:68% to 54:43% fewer incorrect predictions on pairwise relative merit of configurations (tested with 79,800 configuration pairs) than an ANN-based regression model across all DSE scenarios considered (values averaged over all benchmarks for each scenario). We also find that, to achieve the same accuracy as ArchRanker, the ANN often requires three times more training simulations
Funder
Ministry of Science and Technology of the People's Republic of China
National Natural Science Foundation of China
Chinese Academy of Sciences
Publisher
Association for Computing Machinery (ACM)
Cited by
8 articles.
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1. Microarchitecture Design Space Exploration via Pareto-Driven Active Learning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11
2. MiniMalloc: A Lightweight Memory Allocator for Hardware-Accelerated Machine Learning;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4;2023-03-25
3. A design space exploration method for cryptographic processors;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25
4. N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis;Arabian Journal for Science and Engineering;2022-08-20
5. A Memetic Algorithm-Based Design Space Exploration for Datapath Resource Allocation During High-Level Synthesis;Journal of Circuits, Systems and Computers;2019-03-15