Opportunistic compression for direct-mapped DRAM caches-Reference-Cited by-同舟云学术

Opportunistic compression for direct-mapped DRAM caches

Published:2018-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Symposium on Memory Systems
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Author:

Alameldeen Alaa R.¹,Agarwal Rajat¹

Affiliation:

1. Intel Corporation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3240302.3240429

Reference26 articles.

1. Moinuddin K. Qureshi and Gabriel H. Loh "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design " In Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45). Vancouver B.C. Canada pp. 235--246 2012. 10.1109/MICRO.2012.30 Moinuddin K. Qureshi and Gabriel H. Loh "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design " In Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45). Vancouver B.C. Canada pp. 235--246 2012. 10.1109/MICRO.2012.30

2. Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

3. DICE

4. Alaa R Alameldeen and David A Wood. 2004 "Frequent pattern compression: A significance-based compression scheme for L2 caches " Dept. Comp. Scie. Univ. Wisconsin-Madison Tech. Rep 1500 (2004). Alaa R Alameldeen and David A Wood. 2004 "Frequent pattern compression: A significance-based compression scheme for L2 caches " Dept. Comp. Scie. Univ. Wisconsin-Madison Tech. Rep 1500 (2004).

5. C-Pack: A High-Performance Microprocessor Cache Compression Algorithm

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