Cocoa
Author:
Affiliation:
1. Northwestern University
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3240302.3240304
Reference44 articles.
1. Low Vccmin fault-tolerant cache with highly predictable performance
2. A process-tolerant cache architecture for improved yield in nanoscale technologies
3. Energy-efficient cache design using variable-strength error-correcting codes
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1. Enterprise-Class Cache Compression Design;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
2. Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor;Microprocessors and Microsystems;2023-09
3. MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation;IEEE Transactions on Nuclear Science;2022-05
4. Understanding Cache Compression;ACM Transactions on Architecture and Code Optimization;2021-06
5. Cache Tag Array Fault Tolerance Method Based on Redundancy and Similarity of Adjacent Cache Line Tag Bits;International Conference on Frontiers of Electronics, Information and Computation Technologies;2021-05-21
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