Cross Processor Cache Attacks

Author:

Irazoqui Gorka1,Eisenbarth Thomas1,Sunar Berk1

Affiliation:

1. Worcester Polytechnic Institute, Worcester, MA, USA

Funder

National Science Foundation

Publisher

ACM

Reference40 articles.

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2. Fix Flush and Reload in RSA. https://lists.gnupg.org/pipermail/gnupg-announce/2013q3/000329.html. Fix Flush and Reload in RSA. https://lists.gnupg.org/pipermail/gnupg-announce/2013q3/000329.html.

3. HyperTransport Technology white paper. http://www.hypertransport.org/docs/wp/ht_system_design.pdf. HyperTransport Technology white paper. http://www.hypertransport.org/docs/wp/ht_system_design.pdf.

4. Increasing Performance and Introducing CoreLink CCI-500. https://community.arm.com/groups/processors/blog/2015/02/03/extended-system-coherency--part-3--corelink-cci-500. Increasing Performance and Introducing CoreLink CCI-500. https://community.arm.com/groups/processors/blog/2015/02/03/extended-system-coherency--part-3--corelink-cci-500.

5. Intel QuickPath Architecture. http://www.intel.com/pressroom/archive/reference/whitepaper_QuickPath.pdf. Intel QuickPath Architecture. http://www.intel.com/pressroom/archive/reference/whitepaper_QuickPath.pdf.

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1. Non-Fusion Based Coherent Cache Randomization Using Cross-Domain Accesses;Proceedings of the 19th ACM Asia Conference on Computer and Communications Security;2024-07

2. TLTracer: Dynamically Detecting Cache Side Channel Attacks with a Timing Loop Tracer;ICC 2024 - IEEE International Conference on Communications;2024-06-09

3. Timing Side-channel Attacks and Countermeasures in CPU Microarchitectures;ACM Computing Surveys;2024-04-09

4. ZeroShield: Transparently Mitigating Code Page Sharing Attacks With Zero-Cost Stand-By;IEEE Transactions on Information Forensics and Security;2024

5. MARF: A Memory-Aware CLFLUSH-Based Intra- and Inter-CPU Side-Channel Attack;Lecture Notes in Computer Science;2024

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