An FPGA-Based Architecture for High-Speed Compressed Signal Reconstruction

Abstract

Compressive Sensing (CS) is an emerging research area that allows efficient signal acquisition under the sub-Nyquist rate while still promising reliable data recovery. However, practical applications of CS in hardware platforms are limited as signal reconstruction is still challenging due to its high computational complexity, especially for autonomous real-time signal recovery. In this article, we propose an algorithmic transformation technique referred to as Matrix Inversion Bypass (MIB) to improve the signal recovery efficiency of the Orthogonal Matching Pursuit (OMP)-based CS reconstruction. The basic idea of MIB is to decouple the computations of intermediate signal estimates and matrix inversions, thereby enabling parallel processing of these two time-consuming operations in the OMP algorithm. The proposed MIB naturally leads to a parallel architecture for high-speed dedicated hardware implementations. An FPGA-based implementation is developed with the optimized structure aimed at the efficient utilization of hardware resources while realizing high-speed signal recovery. The proposed architecture can perform the signal recovery at up to 1.4 × faster than the OMP-based implementation using almost the same hardware resources.