Affiliation:
1. The University of Texas
2. NVIDIA
Abstract
Increasing transfer rates and decreasing I/O voltage levels make signals more vulnerable to transmission errors. While the data in computer memory are well-protected by modern error checking and correcting (ECC) codes, the clock, control, command, and address (CCCA) signals are weakly protected or even unprotected such that transmission errors leave serious gaps in data-only protection. This paper presents All-Inclusive ECC (AIECC), a memory protection scheme that leverages and augments data ECC to also thoroughly protect CCCA signals. AIECC provides strong end-to-end protection of memory, detecting nearly 100% of CCCA errors and also preventing transmission errors from causing latent memory data corruption. AIECC provides these system-level benefits without requiring extra storage and transfer overheads and without degrading the effective level of data protection.
Publisher
Association for Computing Machinery (ACM)
Reference43 articles.
1. Samsung Electronics Co. "Samsung DDR4 SDRAM " http://www.samsung.com/global/business/semiconductor/file/media/DDR4_Brochure-0.pdf 2013. Samsung Electronics Co. "Samsung DDR4 SDRAM " http://www.samsung.com/global/business/semiconductor/file/media/DDR4_Brochure-0.pdf 2013.
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