Abstract
The memory wall has motivated many enhancements to cache management policies aimed at reducing misses. Cache compression has been proposed to increase effective cache capacity, which potentially reduces capacity and conflict misses. However, complexity in cache compression implementations could increase cache power and access latency. On the other hand, advanced cache replacement mechanisms use heuristics to reduce misses, leading to significant performance gains. Both cache compression and replacement policies should collaborate to improve performance.
In this paper, we demonstrate that cache compression and replacement policies can interact negatively. In many workloads, performance gains from replacement policies are lost due to the need to alter the replacement policy to accommodate compression. This leads to sub-optimal replacement policies that could lose performance compared to an uncompressed cache. We introduce a novel, opportunistic cache compression mechanism, Base-Victim, based on an efficient cache design. Our compression architecture improves performance on top of advanced cache replacement policies, and guarantees a hit rate at least as high as that of an uncompressed cache. For cache-sensitive applications, Base-Victim achieves an average 7.3% performance gain for single-threaded workloads, and 8.7% gain for four-thread multi-program workload mixes.
Publisher
Association for Computing Machinery (ACM)
Reference39 articles.
1. Interactions Between Compression and Prefetching in Chip Multiprocessors
2. ECM: Effective Capacity Maximizer for high-performance compressed caching
3. Business Applications Performance Corporation (BAPCo) "Sysmark 2014 " Whitepaper 2014. https://bapco.com/wp-content/uploads/2015/09/SYSmark2014Whitepaper_1.0.pdf Business Applications Performance Corporation (BAPCo) "Sysmark 2014 " Whitepaper 2014. https://bapco.com/wp-content/uploads/2015/09/SYSmark2014Whitepaper_1.0.pdf
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