Affiliation:
1. CNRS-IRIT-University of Toulouse, Toulouse, France
Abstract
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-case Execution Time (WCET) analysis methods tend to scale poorly to modern hardware architectures. As a result, a trade-off must be found between the duration and the precision of the analysis, leading to an overestimation of the WCET bounds. In turn, this reduces the schedulability and resource usage of the system. In this article, we present a new data structure to speed up the analysis: the
eXecution Decision Diagram
(XDD), which is an ad hoc extension of
Binary Decision Diagrams
tailored for WCET analysis problems. We show how XDDs can be used to represent efficiently execution states in a modern hardware platform. Moreover, we propose a new process to build the
Integer Linear Programming
system of the
Implicit Path Enumeration Technique
using XDD. We use benchmark applications to demonstrate how the use of an XDD substantially increases the scalability of WCET analysis and the precision of the obtained WCET.
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
2 articles.
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1. Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
2. Runtime WCET Estimation Using Machine Learning;Proceedings of the 29th Annual International Conference on Mobile Computing and Networking;2023-10-02