Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
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Published:2009-12
Issue:1
Volume:15
Page:1-22
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ISSN:1084-4309
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Container-title:ACM Transactions on Design Automation of Electronic Systems
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language:en
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Short-container-title:ACM Trans. Des. Autom. Electron. Syst.
Author:
Pomeranz Irith1,
Reddy Sudhakar M.2
Affiliation:
1. Purdue University, W. Lafayette, IN
2. University of Iowa
Abstract
In enhanced-scan circuits, a two-pattern test <
t
i
,
t
j
> for a transition fault can be obtained by using a test
t
j
that detects a stuck-at fault, and preceding it by a test
t
i
that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test <
t
i
,
t
j
> based on stuck-at tests
t
i
and
t
j
, it is not always possible to guarantee that the combination of
t
i
and
t
j
will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.
Funder
Semiconductor Research Corporation
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications