Approximate Spintronic Memories

Abstract

Various applications, such as multimedia, machine learning, and signal processing, have a significant intrinsic error resilience. This makes them preferable for approximate computing as they have the ability to tolerate computations and data errors along with producing acceptable outputs. From the technology perspective, emerging technologies with inherent non-determinism and high failure rates are candidates for the realization of approximate computing. Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM due to its high density, scalability, and zero-leakage. The write operation in this technology is inherently stochastic and increases the rate of write errors. Moreover, this technology is associated with other failure mechanisms such as read-disturb and failures due to data retention. These errors are highly dependent on the STT-MRAM parameters (i.e., thermal stability, read/write current, and read/write latency), which varies with the operating temperature and the process variation effects. Fast and energy-efficient STT-MRAM designed for on-chip memories can be easily achieved by relaxing the device parameters at the cost of increased error rate, which can be addressed by approximating memory accesses. In this work, a detailed study of reliability and gains (i.e., performance and energy) tradeoff at the device and system-level of the STT-MRAM-based data cache system is presented in the scope of approximate memories.