Author:
Agarwal Rishi,Garg Pranav,Torrellas Josep
Cited by
8 articles.
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1. Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy;ACM Transactions on Design Automation of Electronic Systems;2015-12-02
2. Transactional Memory for Reliability;Transactional Memory. Foundations, Algorithms, Tools, and Applications;2015
3. Globally precise-restartable execution of parallel programs;Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation;2014-06-09
4. Globally precise-restartable execution of parallel programs;ACM SIGPLAN Notices;2014-06-05
5. Architectural Support for Fault Tolerance in a Teradevice Dataflow System;International Journal of Parallel Programming;2014-05-29